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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM 1M X 8 bit
GENERAL DESCRIPTION
BS62LV8005
* Wide Vcc operation voltage : 4.5V ~ 5.5V * Very low power consumption : Vcc = 5V C-grade: 45mA (Max.) operation current I -grade: 50mA (Max.) operating current 3uA (Typ.) CMOS standby current * High speed access time : -55 55ns (Max) at Vcc = 5V -70 70ns (Max) at Vcc = 5V * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Fully static operation * Data retention supply voltage as low as 1.5V * Easy expansion with CE1, CE2 and OE options
The BS62LV8005 is a high performance, very low power CMOS Static Random Access Memory organized as 1,048,576 words by 8 bits and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 3uA and maximum access time of 55ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable(CE2) and active LOW output enable (OE) and three-state output drivers. The BS62LV8005 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV8005 is available in 44 pin TSOP2 and 48-pin BGA type.
PRODUCT FAMILY
PRODUCT FAMILY BS62LV8005EC BS62LV8005BC BS62LV8005EI BS62LV8005BI OPERATING TEMPERATURE +0 O C to +70O C -40 O C to +85O C Vcc RANGE 4.5V ~ 5.5V 4.5V ~ 5.5V SPEED ( ns )
Vcc=5V
( I CCSB1, Max )
POWER DISSIPATION STANDBY Operating
( I CC , Max )
PKG TYPE TSOP2-44 BGA-48-0810 TSOP2-44 BGA-48-0810
Vcc=5V
Vcc=5V
55 / 70 55 / 70
30uA 50uA
45mA 50mA
PIN CONFIGURATIONS
A4 A3 A2 A1 A0 CE1 NC NC DQ0 DQ1 VCC GND DQ2 DQ3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 5 6 A5 A6 A7 OE CE2 A8 NC NC DQ7 DQ6 GND VCC DQ5 DQ4 NC NC A9 A10 A11 A12 A13 A14
FUNCTIONAL BLOCK DIAGRAM
BS62LV8005EC BS62LV8005EI
A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4
Address Input Buffer
22
Row Decoder
2048
Memory Array 2048 X 4096
4096 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 CE2 WE OE Vdd Gnd 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 512 Column Decoder 18 Control Address Input Buffer
2
3
4
A
NC
OE
A0
A1
A2
CE2
8
Data Output Buffer
8
B
NC
NC
A3
A4
CE1
NC
C
D0
NC
A5
A6
NC
D4
D
VSS
D1
A17
A7
D5
VCC
E
VCC
D2
VCC
A16
D6
VSS
A11A9 A8 A3 A2 A1 A0A10 A19
F
D3
NC
A14
A15
NC
D7
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV8005
48-Ball CSP top View
1
Revision 2.4 April 2002
BSI
PIN DESCRIPTIONS
BS62LV8005
Function
These 20 address inputs select one of the 1,048,576 x 8-bit words in the RAM CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. is
Name
A0-A19 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output Ports Vcc Gnd
These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
TRUTH TABLE
MODE Not selected (Power Down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O OPERATION High Z High Z DOUT DIN Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER
Terminal Voltage Respect to GND with
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 O C to +70 O C -40 C to +85 C
O O
Vcc
4.5V ~ 5.5V 4.5V ~ 5.5V
Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
C C
O
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CIN CDQ
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
10 12
pF pF
1. This parameter is guaranteed and not tested.
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DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER NAME
VIL VIH IIL IOL VOL VOH ICC ICCSB ICCSB1
BS62LV8005
TEST CONDITIONS
Vcc=5V
PARAMETER
Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL Standby Current-CMOS
MIN.
-0.5 2.2 ---2.4 ----
TYP. (1)
--------3
MAX.
0.8 Vcc+0.2 1 1 0.4 -45 2 30
UNITS V V uA uA V V mA mA uA
Vcc=5V
Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIH or CE2 = VIL or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA CE1= VIL, CE2= VIH, IDQ = 0mA, (3) F = Fmax CE1 = VIH, CE2= VIL, IDQ = 0mA CE1 Vcc-0.2V, CE2 0.2V VIN Vcc - 0.2V or VIN 0.2V
Vcc=5V Vcc=5V
Vcc=5V
Vcc=5V
Vcc=5V
1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
VDR
PARAMETER
Vcc for Data Retention
TEST CONDITIONS
CE1 Vcc - 0.2V or CE2 VIN Vcc - 0.2V or VIN CE1 VIN 0.2V or 0.2V
MIN.
1.5
TYP. (1)
--
MAX.
--
UNITS
V
ICCDR tCDR tR
Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Vcc - 0.2V or CE2 0.2V Vcc - 0.2V or VIN 0.2V
-0
0.4 ---
2.5 ---
uA ns ns
See Retention Waveform
TRC (2)
1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode VDR 1.5V
Vcc
VIH
Vcc
Vcc
t CDR
CE1 Vcc - 0.2V
tR
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
VDR
1.5V
Vcc
t CDR
tR
CE2 0.2V
CE2
VIL
VIL
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BSI
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0 5ns 0.5Vcc
WAVEFORM INPUTS
BS62LV8005
KEY TO SWITCHING WAVEFORMS
OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY
AC TEST LOADS AND WAVEFORMS
5.0V
1928
5.0V OUTPUT
1928
,
100PF
INCLUDING JIG AND SCOPE
5PF 1020
INCLUDING JIG AND SCOPE
1020
FIGURE 1A
THEVENIN EQUIVALENT 667
FIGURE 1B
OUTPUT
1.73V
ALL INPUT PULSES
Vcc GND
10%
90% 90%
10%
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC , Vcc = 5V )
READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z
Output Disable to Output Address Change
BS62LV8005- 70 MIN. TYP. MAX.
BS62LV8005- 55 MIN. TYP. MAX.
UNIT
ns ns ns ns ns ns ns ns ns ns
t AVAX t AVQV t E1LQV t E2LQV t GLQV t ELQX t GLQX t EHQZ t GHQZ t AXOX
t RC t AA t ACS1 t ACS2 t OE t CLZ t OLZ t CHZ t OHZ t OH
70 -(CE1) (CE2)
-----------
-70 70 70 35 --35 30 --
55 ----10 10 0 0 10
-----------
-55 55 55 30 --30 25 --
---10 10 0 0 10
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SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS62LV8005
t RC
ADDRESS
t
D OUT
t
OH
AA
t OH
READ CYCLE2 (1,3,4)
CE2
t t
ACS2
ACS1
CE1
t
D OUT
(5) CLZ
t
CHZ
(5)
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
OE
AA
t
CE2
OE
t
OH
t t t t
(5) CLZ
ACS2
CE1
OLZ
ACS1
t t
OHZ CHZ
(5)
(1,5)
D OUT
NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.
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AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC , Vcc = 5.0V )
WRITE CYCLE
JEDEC PARAMETER PARAMETER NAME NAME DESCRIPTION
Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End ot Write to Output Active (CE2,CE1 , WE) BS62LV8005-70 MIN. TYP. MAX.
BS62LV8005
BS62LV8005-55 MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns
tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLOZ tDVWH tWHDX tGHOZ tWHQX
t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OHZ t OW
70 70 0 70 35 0 0 30 0 0 5
------------
------30 --30 --
55 55 0 55 30 0 0 25 0 0 5
------------
------25 --25 --
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
ADDRESS
t
WC
t WR
OE
(3)
CE2
(5)
t CW
CE1
(5)
(11)
t AW
WE
(3)
t AS
(4,10)
t WP
(2)
t OHZ
D OUT
t DH t DW
D IN
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WRITE CYCLE2 (1,6)
BS62LV8005
t WC
ADDRESS
CE2
(11)
CE1
(5)
t
CW
t
WE
AW
t WP
t
WR
(3)
(2)
t AS
(4,10)
t DH
(7) (8)
t WHZ
D OUT
t DW t
DH
(8,9)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
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BSI
ORDERING INFORMATION
BS62LV8005
BS62LV8005
XX
YY
SPEED 55: 55ns 70: 70ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 B: BGA-48-0810
PACKAGE DIMENSIONS
TSOP2-44
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Revision 2.4 April 2002
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PACKAGE DIMENSIONS (continued)
0.05
NOTES:
BS62LV8005
0.25
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
SIDE VIEW
D 0.1 D1
N 48 D 10.0 E 8.0 D1 5.25 E1 3.75 e 0.75
SOLDER BALL
0.35
0.05
e
E1 VIEW A
48 mini-BGA (8 x 10mm)
E
0.1
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Revision 2.4 April 2002
BSI
REVISION HISTORY
Revision
2.2 2.3 2.4
BS62LV8005
Description
2001 Data Sheet release
Date
Apr. 15, 2001
Note
Modify Standby Current (Typ. and Jun. 29, 2001 Max.) Modify some AC parameters. April,11,2002
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Revision 2.4 April 2002

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